In a source-synchronous architecture, one integrated circuit is the source of the clock and data for another integrated circuit. The integrated circuit providing the clock and data is denoted as the source integrated circuit whereas the integrated circuit (or circuits) receiving the clock and data is denoted as a receiving integrated circuit. Because the source integrated circuit forwards the clock to the receiving integrated circuit, such a system is also referred to as a forwarded clock architecture. Source-synchronous systems are popular because the process, voltage, and temperature (PVT) variations for the forwarded clock will generally match the PVT variations in the data. In a double-data-rate (DDR) architecture, the receiving integrated circuit delays the clock in a delay element to allow for proper setup time of the data with regard to a resulting delayed version of the clock. For example, if the clock is delayed by T/4 relative to the data, where T is the clock period, the optimal amount of setup time is achieved in a DDR system.
The delay element or circuit in the receiving integrated circuit is typically an adjustable delay element so that the adjustable delay element can be controlled to accommodate PVT variations. The control of the adjustable delay element to achieve a desired amount of delay may be accomplished using a master/slave control architecture such as shown in FIG. 1A for a slave device 100 and a master device 105. Master device 105 includes a copy of an adjustable delay element (not illustrated) in slave device 100 that is calibrated through, for example, a phase-locked loop (PLL). Master device 105 calibrates its adjustable delay element to the desired delay such as T/4 and commands slave device 100 to use the same setting on its adjustable delay element. Since master device 105 and slave device 100 both have the same adjustable delay elements, the applied settings in slave device 100 should achieve the same delay as was calibrated in master device 105.
An alternative to a master/slave architecture is a dual-master architecture such as shown in FIG. 1B for a pair of dual-master devices 110 and 115. Each dual-master device 110 and 115 includes an adjustable delay element and alternates in cycles between functioning as a calibrating element or a service element. At any given cycle, one of the dual-master devices is calibrating its adjustable delay element whereas the remaining dual-master device (having been calibrated in the preceding cycle) functions as the service element such that its adjustable delay element delays the desired signal. In the particular cycle for FIG. 1B, dual-master device 115 is calibrating whereas dual-master device 110, having already been calibrated in a previous cycle, functions as a service element. Since each dual-master device independently calibrates its adjustable delay element, dual-master device 110 need not include a copy of the adjustable delay element in dual-master device 115. However, it is convenient from a design perspective that each dual-master device has an identical adjustable delay element. After a given amount of time in these service and calibrating roles, a new cycle would ensue in which dual-master device 115 would be the service element whereas dual-master device 110 would calibrate.
The dual-master architecture requires a pair of dual-master devices for every delay element instantiation. In contrast, only a single master device is required in a master/slave architecture. For example, there could be ten slave devices 100 controlled by a single master device 105 (for a total of eleven devices). In contrast, the same ten adjustable delay elements would require ten dual-master devices 110 and another ten dual-master devices 115 in a dual-master architecture (a total of twenty devices).
Although a master-slave architecture is thus much denser with regard to the instantiation of a plurality of adjustable delay elements in an integrated circuit, the control is open loop in that an assumption is made that the same settings (e.g., a control voltage, current, or a digital code) as determined in master device 105 to produce a calibrated delay will produce the same amount of delay in slave device 100. But there can be process variations across the die from master device 105 to slave device 100 such that the open loop control becomes inaccurate, particularly at higher data rates. Moreover, the localized circuitry around slave device 100 may be different from the local environment for master device 105, which can also make the open loop control inaccurate. In contrast, in a dual-master architecture, a calibrated dual-master device then functions as a service element. So there can be no process variations in a dual-master system. Moreover, the local electrical environment will be substantially the same although local systems may switch on or off during the time a service element functions.
Accordingly, there is a need in the art for an adjustable delay element having the accuracy of a dual-master system while having the density advantages of a master/slave system.